cs.AR · 2026-06-05 · No. 14

Hardware Architecture, 2026-06-05.

1 new papers in cs.AR. Titles, authors, abstracts. Links to arXiv. Want this in your inbox every morning? Subscribe →

01 — The papers

1 entries
  1. 01

    ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training

    Haihang Xia, Xinyu Zhao, Xuecheng Wang, John Goodenough, Charith Abhayaratne, Panagiotis A. Panagiotou, Chunyi Song,...

    cs.AR · cs.AI · cs.NE

    Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications. However, the large number of synaptic connections in SNNs leads to intensive weight-update computation by on-chip learning algorithms during training, resulting in substantial hardware resource utilization and energy consumption. Among existing SNN learning...

    arxiv.org/abs/2606.06159 · PDF

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