arXiv cs.AR
Hardware Architecture daily digest.
23 past editions, oldest first by date. Atom feed → · all categories
01 — Past editions
most recent first- 2026-07-19 NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference 4 papers · No. 58
- 2026-07-18 NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference 4 papers · No. 57
- 2026-07-17 NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference 4 papers · No. 56
- 2026-07-16 Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by... 1 papers · No. 55
- 2026-07-12 FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with... 2 papers · No. 51
- 2026-07-11 FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with... 2 papers · No. 50
- 2026-07-10 FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with... 2 papers · No. 49
- 2026-07-01 FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers 2 papers · No. 40
- 2026-06-30 COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU... 2 papers · No. 39
- 2026-06-29 Agentic Hardware Design as Repository-Level Code Evolution 2 papers · No. 38
- 2026-06-18 PuDGhost: Experimental Analysis of Computation Result Corruption in... 1 papers · No. 27
- 2026-06-17 MIVE: A Minimalist Integer Vector Engine for Softmax LayerNorm and RMSNorm... 1 papers · No. 26
- 2026-06-16 TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient... 2 papers · No. 25
- 2026-06-14 SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network... 1 papers · No. 23
- 2026-06-13 SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network... 1 papers · No. 22
- 2026-06-12 SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network... 1 papers · No. 21
- 2026-06-10 Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA 1 papers · No. 19
- 2026-06-09 An 84-Format Numeric Catalog with Bit-Exact Conformance Vectors: A... 1 papers · No. 18
- 2026-06-07 ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training 1 papers · No. 16
- 2026-06-06 ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training 1 papers · No. 15
- 2026-06-05 ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training 1 papers · No. 14
- 2026-05-23 NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest... 2 papers · No. 8
- 2026-05-22 NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest... 2 papers · No. 7
Colophon
Set in Georgia, with system sans for interface chrome and a monospaced stack for code and paper identifiers. Sole accent: amber
#D99C5E. Built and served on an always-free VM. The masthead is set 14% letterspaced because newspapers do that and it works.