cs.AR · 2026-07-20 · No. 59
Hardware Architecture, 2026-07-20.
1 new papers in cs.AR. Titles, authors,
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01 — The papers
1 entries-
01
RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm
Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie
cs.AR · cs.AI · cs.LG
Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models....
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