cs.AR · 2026-07-26 · No. 65

Hardware Architecture, 2026-07-26.

1 new papers in cs.AR. Titles, authors, abstracts. Links to arXiv. Want this in your inbox every morning? Subscribe →

01 — The papers

1 entries
  1. 01

    Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core

    Benjamin Hubinet, Pierre-Alain Moellic, Olivier Savry, Olivier Potin, Jean-Baptiste Rigaud

    cs.AR · cs.AI

    By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training on resource-constrained RISC-V single-core. Our approach allows memory footprint reduction by about 50% as compared to using float32 and with minimal model performance degradation. We also facilitate transfer learning and fine-tuning scenarios by incorporating...

    arxiv.org/abs/2607.21130 · PDF

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