cs.AR · 2026-07-30 · No. 69

Hardware Architecture, 2026-07-30.

2 new papers in cs.AR. Titles, authors, abstracts. Links to arXiv. Want this in your inbox every morning? Subscribe →

01 — The papers

2 entries
  1. 01

    Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices

    Harvey Samuel George Johnson, Sendy Phang

    cs.AR · cs.CE · cs.ET · cs.LG · physics.app-ph

    This project aimed to develop a novel reservoir compute (RC) implementation framework targeting high-speed operation and integration with CMOS digital logic. With the target workload of branch prediction (BP) for multistage pipelined central pro-cessing unit (CPU) cores. For this, a novel memristor based RC design framework was developed within the context of the workload requirements. This was then implemented in simulation using industry...

    arxiv.org/abs/2607.27140 · PDF

  2. 02

    LLMET: Enabling Cross-Layer Evaluation of Emerging M3D Memories for Energy-Efficient LLM Serving

    Ming-Yen Lee, Hanchen Yang, Faaiq Waqar, Harsono Simka, Tushar Krishna, Muhammed Ahosan Ul Karim, Shimeng Yu

    cs.AR · cs.AI · cs.ET · cs.LG

    The energy consumption of Large Language Model (LLM) serving is becoming a major system challenge as deployment scales, driven by hardware power and thermal constraints and rising electricity costs. A key contributor to chip energy dissipation is data movement between limited on-chip cache and off-chip High Bandwidth Memory (HBM). Meanwhile, emerging memory technologies such as monolithic 3D (M3D) integration of cache memories at the...

    arxiv.org/abs/2607.26491 · PDF

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