cs.AR · 2026-08-19 · No. 89

Hardware Architecture, 2026-08-19.

1 new papers in cs.AR. Titles, authors, abstracts. Links to arXiv. Want this in your inbox every morning? Subscribe →

01 — The papers

1 entries
  1. 01

    NeuroAbs: A Neuro-Symbolic RTL Abstraction Framework for Property Checking Acceleration

    Zhiyuan Yan, Xiaofeng Zhou, Ziyue Zheng, Ziyi Yang, Wenbin Che, Wei Zhang, Yangdi Lyu, Hongce Zhang

    cs.AR · cs.AI · cs.SE

    Formal verification is a crucial technique for ensuring the functional correctness of hardware designs. In the context of property checking, a key challenge is how to efficiently prove a user-specified property in the face of increasingly complex RTL designs. To address this challenge, abstraction techniques are often employed to reduce system complexity and accelerate the verification process. However, prior RTL abstraction methods either...

    arxiv.org/abs/2608.17304 · PDF

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