cs.AR · 2026-08-20 · No. 90

Hardware Architecture, 2026-08-20.

1 new papers in cs.AR. Titles, authors, abstracts. Links to arXiv. Want this in your inbox every morning? Subscribe →

01 — The papers

1 entries
  1. 01

    Coverage-Driven RTL Assertion Generation with Formal Exploration and Neuro-Symbolic Refinement

    Zhiyuan Yan, Ziyue Zheng, Hongce Zhang

    cs.AR · cs.AI

    Hardware functional verification relies on high-quality assertions to expose design bugs and establish confidence in Register Transfer Level (RTL) designs. Yet existing assertion mining methods still struggle to produce complete and reliable assertion sets: random or limited traces fail to cover hard-to-reach behaviors, and one-shot generation provides little feedback about what remains unverified or how the assertion set should be improved....

    arxiv.org/abs/2608.18482 · PDF

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