cs.AR · 2026-09-05 · No. 106

Hardware Architecture, 2026-09-05.

1 new papers in cs.AR. Titles, authors, abstracts. Links to arXiv. Want this in your inbox every morning? Subscribe →

01 — The papers

1 entries
  1. 01

    LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

    Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu

    cs.AR · cs.AI · cs.LG

    As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire Load Models (WLMs), while recent spectral-based placement predictors often neglect the inherent hierarchical logic depth and signal flow of...

    arxiv.org/abs/2609.03594 · PDF

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